 |
1. Structure |
1.1 Basic
Structure
Active Matrix VFDs are a special type of Chip-in-Glass
(CIG) VFD. They contain small silicon chips about 5x5mm in size which
include the phosphor matrix, driver and memory functions.
In order to
construct a wide display area, these small square silicon chips are
precisely "tiled" on the glass plate with each having a 16x16 dot matrix
phosphor pattern precisely formed on the top surface.
Only 2 chips can be
put vertically (Y direction) due to the space required for wire bonding as
shown in Fig. 1. |
Fig.1 Active Matrix VFD using 'Tiled' Silicon Chips
|
As with conventional VFDs,
the Active matrix VFDs have cathode (filaments) to emit electrons, mesh
grids to diffuse electrons, and anodes coated with phosphor to which
attract electrons and emit light.
As with other CIG VFDs, a
reduced number of lead pins contribute to easy assembly compared to the
conventional graphic VFDs.
The Active Matrix technology has only
one grid structure allowing a high resolution graphic display without the
need for the complex multiple grid structure found in other graphic
VFDs. |
|
| |
|
1.2 The Silicon
Chip
The silicon chip used in Active Matrix VFDs contains a 256 bit
(16 x 16 matrix) driver, latch and shift-register circuit as shown in Fig.
4. which is similar to ordinary discrete VFD driver ICs. When the chips
are formed into a large graphic array, the serial data output from each
chip is fed to serial input of the next chip and can therefore be
controlled as "one" large shift register and driver circuit. Once data is
loaded into the shift registers it can remain unchanged until the image on
the display is required to be changed. This makes it possible to control
the display from the simplest of
CPUs.
|
Fig. 4 Silicon Chip Block Diagram |
2. Power Supply |
2.1
Supply Voltages
The supply voltage requirement of active
matrix VFDs is a filament supply, (as in ordinary VFDs), a logic supply
voltage "VDD1" and a display supply voltage "VDD2". The table lists the
typical termination names and function. Please check the individual
specification for current consumption and actual voltage
value.
|
| Symbol |
Terminal |
Voltage |
Function |
Notes |
| Ef |
F1-F2 |
Filament |
Electron emission |
AC |
| VDD1 |
VDD1 |
Logic Supply |
For logic in silicon chip |
5V |
| VDD2 |
VDD2 |
Display Supply |
Phosphor excitation |
15V |
| EC |
G |
Grid Voltage |
Electron diffusion |
15V |
| EK |
- |
Filament Bias |
Emission Cutoff |
0.6V |
| GND |
GND |
Ground 0V |
Ground of VDD1, VDD2 |
0V |
|
2.2
Power Supply Circuit
The grid and anode supply voltage is typically 12V to
15V DC and applied to G directly and to VDD2 via a limiting resistor of
22R to 100R to prevent current surges causing false operation. Please
refer to the specification for the recommended value. Do not fit a
capacitor between the VDD2 input and GND as this will obsolete the
resistor.
|
The filament
voltage applied to F1,F2 of the VFD is critical in terms of it's effect on
life-time if operated outside the specified operating voltages. The
filament transformer is normally supplied with a centre tap which is
biased at 0.6VDC above GND. Too high a bias may cause uneven
illumination.
The logic supply terminal VDD1 should have a
noise filtering capacitor of 0.01uF to 0.22uF mounted between it and GND
to prevent false operation. |
| Although
adjustment of VDD2 will change the display brightness, it is preferred to
use pulse width control applied to the enable input to prevent uneven
illumination at low brightness. This method is described
later. |
| |
2.3
Power Supply Sequence
2 types of power supply sequence apply at
power ON and power OFF due to the different internal construction of the
silicon chips employed in Active Matrix VFDs. The chips may become damaged
if the sequence is not followed.
|
|
TYPE 1 (Dot
pitch=0.347mm Type)
| Power
On |
"VDD1" and "VDD2"
should be ON at the same time, or "VDD1" should be ON after
"VDD2" is ON.
The VDD2"-VDD1" delay time should be small as
possible (Less than 200msec.). |
 |
| Power
Off |
"VDD1" and "VDD2"
should be OFF at the same time, or "VDD2" should be OFF after
"VDD1" is OFF.
The VDD1"-VDD2" delay time should be small
as possible (Less than 200msec.). |
TYPE 2 (Dot
pitch=0.308mm Type)
| Power
On |
"VDD1" and "VDD2"
should be ON at the same time, or "VDD2" should be ON after
"VDD1" is ON. |
 |
| Power
Off |
"VDD1" and "VDD2"
should be OFF at the same time, or "VDD1" should be OFF after
"VDD2" is
OFF. |
|
|
There is
no specific restriction for the on/off timing between "VDD1"/"VDD2" and
the filament voltage Ef.
Please note that it takes one to two
seconds for the filament to rise to its optimum temperature after the
filament voltage is applied, during which time the brightness will
rise.. |
3. Interface |
3.1
Interface Signals
The interface of Active Matrix VFDs is
"C-MOS" level clock synchronized serial data.
The functions are
described in the adjacent. |
| Terminal |
Function Note: "H"=High, "L"=Low |
| CLK |
Shift Register
Clock |
Data Read and Shift at
Rising Edge, fCLK=4MHz MAX. |
| SI |
Serial Data
Input |
"H"=Dot ON, "L"=Dot
OFF |
| SO |
Serial Data
Output |
Keep open if not
use. |
| LAT |
Data Latch
Control |
"H"=Through,
"L"=Latch |
| EN |
Display Enable
Control |
"H" or "OPEN"=Display
ON, "L"=Display OFF |
|
| |
3.2
Interface Characteristics
This table shows the basic threshold
voltages and response times of the interface.
Please check the
individual specification for details. |
| Symbol |
Item |
Condition |
MIN |
TYP |
MAX |
Unit |
| VIH |
H-level Input
Voltage |
|
3.7 |
- |
VDD1 |
V |
| VIL |
L-level Input
Voltage |
|
0 |
- |
1.3 |
V |
| IIH |
H-level Input
Current |
VIH=VDD1 |
- |
- |
0.5 |
uA |
| IIL |
L-level Input
Current |
VIL=0V |
See
spec sheet |
uA |
| VOH |
H-level
Output Voltage |
SO,
IOH=-40uA |
4.6 |
- |
- |
V |
| VOL |
L-level
Output Voltage |
SO,
IOH=40uA |
- |
- |
0.6 |
V |
| tr,
tf |
Data
Output Rise/Fall Time |
CL=10pF |
- |
10 |
- |
ns |
| tPD |
CLK to SO
Delay Time |
CL=10pF |
50 |
88 |
125 |
ns |
| fCLK |
Clock
Frequency |
|
- |
- |
4 |
MHz |
|
| |
|
3.3
Interface Timing
Fig 8 shows the timing waveforms for the
interface signals. Please check the individual specification for
details. |
Fig. 8 Basic Interface Timing Chart |
| |
|
3.3
CPU Interface
A single line chip array Active Matrix VFD
typically has one serial I/O and can be controlled by 4 ports on the
CPU. |
Fig.
9 Single Chip Array Application Circuit |
| |
|
A dual
line chip array type has two serial I/Os, "a" for the upper array and "b"
for the lower array.
This dual line array type can be
controlled by one I/O by connecting the "SOa" output to "SIb" input as
shown in Fig. 10 |
Fig.10 Dual Chip Array Application
Circuit |
4. Control Procedure |
4.1 Data
Transfer Protocol
Figure 11 and 12 show an example of the data
transfer protocol for an Active Matrix VFD with 16 silicon chips in a
single line which produces a graphic display of 256x16 dots. The inputs
and outputs of each chip are cascaded to form one long shift register
chain of 4096 bits. |
|
Fig. 11 Data Transfer of 4096 bits
|
|
|
Each bit in shift register is
assigned to each dot on the silicon chip on a one-on-one basis. The
relevant assignment order is explained in "Dot Assignment and Shift
Register" or "Data Sending Order" on the individual specification.
Each
dot is turned on/off by setting each related bit in shift register as
"High" = ON or "Low" = OFF.
The silicon chip has a data latch control
function, so the content of latched data is kept until it is latched
again. This allows one image to be displayed while the next image is being
loaded.
|
|
Fig.12 Dot Assignment to Shift Register Bit on Each Chip
|
| |
4.2
Display Enable
The silicon chip of the Active Matrix VFD has a
display on/off enable control function. By using the enable control, the
whole display can be turned on/off or made to blink irrespective of the
data set in the shift register. When EN = High or Open, the display is ON
and when EN is Low the display is OFF.
To avoid miss-transfer of data
due to switching noise, do not change "EN" from "Low" to "High" or "High"
to "Low" when sending data to the shift register. Please refer to the
timing in Fig.13
|
Fig.13 Enable Control Timing
|
|
4.3 Brightness
Control
The brightness level (intensity of the display) can be
adjusted using the enable control (EN) by applying an enable pulse with a
minimum frequency of 100Hz in order to avoid display flicker. The
duty factor of the enable pulse determines the the brightness level
according to the formula:
Brightness = tEN/Tx100(%). |
 |
5. Custom Design Guidance |
The range
of Noritake Itron standard Active Matrix VFD's covers most of the popular
dot configurations. If you do not find a suitable configuration, we will
be pleased to consider a custom design. Please use the following general
design guide for your initial request.
5.1
Number of Silicon Chips and Glass Package Size
There are 2 types of
silicon chips available with dot pitches of 0.347mm and 0.308mm. Both of
them have a 16 x 16 dot matrix configuration per chip. The minimum number
of the chips per VFD tube is "ONE", and the maximum is up to about 20
chips per single array or 40 chips for a dual array (2 rows). The
relationship between the number of chips and the outer dimension of glass
package is shown in the following table.
|
|
Dot Pitch
> |
0.347mm |
0.308mm |
No.
of
Chips |
Dot
Config. |
Display
Area
(mm) |
Outer
Dimension
LxH(mm) |
Standard
Item |
Display
Area
(mm) |
Outer
Dimension
LxH(mm) |
Standard
Item |
| 4 |
64x16 |
|
|
|
19.6x4.8 |
45.0x16.0 |
MW06416DB |
| 5 |
80x16 |
|
|
|
24.5x4.8 |
50.0x16.0 |
|
| 6 |
96x16 |
|
|
|
29.4x4.8 |
55.0x16.0 |
|
| 8 |
128x16 |
44.2x5.4 |
70.0x17.0 |
MW12816A |
39.3x4.8 |
62.0x16.0 |
MW12816DB |
| 12 |
192x16 |
|
|
|
59.1x4.8 |
85.0x16.0 |
|
| 16 |
256x16 |
88.6x5.4 |
115.0x17.0 |
MW25616L |
78.7x4.8 |
102.0x16.0 |
MW25616NB |
| 4x2 |
64x32 |
|
|
|
19.6x9.7 |
45.0x20.5 |
|
| 5x2 |
80x32 |
|
|
|
24.5x9.7 |
50.0x20.5 |
|
| 8x2 |
128x32 |
44.2x11.0 |
70.0x22.5 |
MW12832D |
39.3x9.7 |
62.0x20.5 |
MW12832GB |
| 12x2 |
192x32 |
|
|
|
59.1x9.7 |
85.0x20.5 |
MW19232BB |
| 16x2 |
256x32 |
88.6x11.0 |
115.0x22.5 |
MW25632C |
78.7x9.7 |
102.0x20.5 |
MW25632EB |
 |
|
| A
new chip is being developed for Q4 2001 which is 32 dots high by 16 dots
wide. |
| |
5.2
Multi line Chip Array
A minimimum space is required between arrays
depending on the position of the bonding area. Please refer to the
following table.
|
| Condtions |
No wire bonding area
between line |
One wire bonding area
between line |
Two wire bonding area
between line |
Minimum
Gap |
|
|
|
|
| |
5.3
Combining with a Conventional VFD Display Pattern
The silicon chips
'C' can be combined with a conventional custom designed VFD pattern which
can be controlled by a CIG (Chip in Glass) driver to maintain a low number
of pin outs as shown in Figure 19. |
Fig.19 Combination with Conventional VFD's Display Patten Pattern |
| |
5.4
Lead Pins
The standard lead pin of an active Matrix VFD is 6.0mm in
length and 2.0mm pitch. The dimensions of standard lead pin is shown in
Figure 20.
Custom lead pins are available upon
request.
|
Fig. 20 Lead
Pin Dimensions |
6. Reliability Test Conditions |
| Basically, the Active Matrix
VFD is subjected to the same reliability test standards "TT-99-3050A" as
the conventional VFD. For details on the test conditions, refer to Vacuum
Fluorescent Display Application Note
APN101. |
7. Precautions On The Handling |
- Since the Active Matrix VFD
contains C-MOS chips, please be cautious of electrostatic discharge
failure. Unpacking of the VFD from the packing tray and mounting or
soldering to the PCB should be conducted in an environment provided with
anti-static measures.
- When the serial output (SO)
terminals are not used, please leave them disconnected.
- Some types of Active Matrix
VFD may come equipped with terminals of the same
designation.
Those terminals with the same designation should
all be connected in parallel.
- Please refer to the power
supply sequence in this application note or individual
specification.
- Insert a noise filtering
capacitor between "VDD1" and "GND".
- Please fit a current
limiting resistor of value 22R to 100R in series with the "VDD2"
input.
|
8. Words Used In Specifications |
Spec. No.
The "Spec
No." shows the revision number for the specification sheet. Each
documented specification carries an area of revision history in the upper
right corner of the top page. The specifications of the standard models
are subject to change without prior notice, so, please check if the
revision number of your specification is the latest version before
evaluating it.
Absolute Maximum Ratings
The "Absolute
Maximum Ratings" refer to values that must not be exceeded in any event.
Using a VFD in excess of the specified rating may lead to its permanent
breakdown. Therefore, high reliability will be secured if special
attention is paid to the design of a power supply circuit, possible
fluctuations in the supply voltage, surrounding components, operating
temperature, environment surges or spikes, etc.
Rating or
Recommended Operating Conditions
The "Rating" or "Recommended
Operating Conditions" represent the specification of a recommended
operating condition that guarantees the operation of the VFD. It also
serves as a test condition for which the product is subjected prior to
shipment from the factory. Therefore, it should be noted that if a VFD is
used in excess of the maximum or minimum rating specified here, its
operation and quality will not generally be guaranteed even when it
remains within the absolute maximum rating.
In addition, this rated
value has been defined assuming the most standard service conditions by
users. However, some may want to study the possibility of using the VFDs
outside the rated value, prompted by a desired individual requirement. In
such a case, please feel free to consult with us, as we may be willing to
discuss the possibility of the proposed specifications.
Block
Diagram
It shows how to connect the power supplies. The basic
circuit used in factory inspection is the same as this
one.
Electrical (and Optical) Characteristics
All of
numbers specified in this section shows the characteristics when the
Active Matrix VFDs are tested under the typical (TYP) operating conditions
unless otherwise noted.
Timing Chart
It shows the AC
characteristics and relationship of interface
operations. |
|
|
