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CL VFDs Application Note APN130

3. INTERFACE

3.1 Interface

The interface of all CL VFD is "C-MOS" level standardized clock-synchronized serial data inputs.

Table 2 lists the functions of the major terminals of the interface. Table 3 summarizes their characteristics. Figure 10 represents the timing carts of these interfaces.

Table 2: Function Table of Interface Terminals

Terminal Function

CLK Shift Register Clock Data Read and Shift at Rising Edge, fCLK=4MHz MAX.

SI Serial Data Input "H"=Dot ON, "L"=Dot OFF

SO Serial Data Output Keep open if not use.

LAT Data Latch Control "H"=Through, "L"=Latch

EN Display Enable Control "H" or "OPEN"=Display ON, "L"=Display OFF

Note: "H"=High, "L"=Low

Table 3 Interface Characteristics

Symbol Item Condition MIN TYP MAX Unit

VIH H-level Input Voltage
3.7 - VDD1 V

VIL L-level Input Voltage
0 - 1.3 V

IIH H-level Input Current CLK,LAT,SI,EN VIH=VDD1 - - 0.5 uA

IIL L-level Input Current VIL=0V See individual sepc sheet uA

VOH H-level Output Voltage SO, IOH=-40uA 4.6 - - V

VOL L-level Output Voltage SO, IOH=40uA - - 0.6 V

tr, tf Data Output Rising/FalingFalling Time CL=10pF - 10 - ns

tPD CLK to SO Delay Time CL=10pF 50 88 125 ns

fCLK Clock Frequency
- - 4 MHz

Note: The function may vary by each item. Please check the specification for details.

Fig.10 Interface Timing Chart

3.2 CPU

The CL VFDs adopts the synchronous serial interface, so the CL VFDs do not require a CPU with high voltage output designed for ordinary VFDs.

3.3 Drive Circuit

Single line chip array type has one serial I/O, and dual line chip array type have two pair of serial I/Os ("a" for upper array, "b" for lower array). Dual line array type can also be controlled by one I/O by connecting "SOa" to "SIb" as shown in the Figure 12.

Fig.11 Application Circuit for Single Line Array Type

Fig.12 Application Circuit for Dual Line Array Type

Back to APN130 Index 4. Control Procedure

APN130