Chip in Glass Driver VFD : BD-VFD
The contents of this document are subject to copyright and may not be amended or included in other documents or media without the express permission of Noritake Co., Limited, Japan.
Revised 29th July 2001.
1. Operation and Structure
Conventional CIG displays require a relatively large additional space for installing driver chips which causes the VFD size to be much larger. The Noritake Itron CIG VFD incorporates compact & high-density driver chips underneath the metal frame supporting the filament. For this reason, Noritake Itron CIG VFDs can be the same size as ordinary VFDs without driver chips. The absence of external driver chips allows for a substantial saving of space in the circuit design of the VFD and reduced assembly costs with improved MTBF capability.
1.1 Basic Structure
As can be seen in Fig. 1, the driver chip is located on the glass plate under the frame, and connected by wire bonding to the electrodes which are located on the glass plate. The data and power supplies to the drivers are connected to the lead pins through the conductive tracks on the plate. The output of the drivers go through the conductive tracks located on the same plate to reach their respective segments (phosphors) and/or grids.
Fig.1 Basic Structure of CIG VFD
1.2 CIG Driver Chip
The CIG VFD incorporates one to four 96-bit, 128-bit or 144bit drivers, depending on the display pattern demanded by the application. Like the driver ICs in ordinary VFDs, the drivers in CIG VFD contain level shifters, latches, and shift registers made of C-MOS FET circuits as shown in Fig. 2.
The devices are less than 10mm in length with very fine bonding pitches along one side which requires Noritake to employ the world’s fastest fine pitch bonding machines.
Fig.2 Logic Diagram of CIG Driver (96bit type)
1.3 CIG VFD Drive Methods
The CIG VFDs can be classified into two types of drive method known as ‘ static’ or ‘ multiplex’ drive, and in multiplex drive there are two interconnection types known as Grid Anode hybrid interlacing or Grid Anode independent. Each type has different driving procedure.
- Static Drive – Each anode driven by a dedicated driver output
- Hybrid Interlace – Anodes and grids combined on one serial driver.
- Independent – Anodes and grids have separate serial drivers.
1.3.1 Static Drive
The static drive type requires each output from the driver to be directly connected to a corresponding segment. The grid voltage is supplied directly from the lead pins to a common grid covering all the anodes without passing through the driver circuits. Static drive has the disadvantage of using a greater number of driver outputs compared to multiplex drive.
It does however offer some important advantages, such as freedom of segment patterning and the dead space for grid division is not necessary. Also, the driving voltage can be 12V and higher brightness can easily be obtained.
Therefore, the static driven CIG VFD is suitable for applications which require flexible segment design, lower power consumption and/or higher brightness. Fig. 3 represents a logic diagram of the static driven CIG VFD with two 96 bit driver chips which can drive a maximum of 192 segments.
Fig.4 Example of Grid Anode Hybrid Interlace Type
Fig.5 Example of Grid Anode Independent Type
2. Power Supply
The power requirements of the CIG VFD are a filament supply (same as ordinary VFDs), logic supply voltage of “VDD1” and display voltage of “VDD2”. The range of values typically required are shown in the following table. Please check the individual product specification for the specific values.
|Ef||F1, F2||Filament, voltage according to specification.||2Vac to, 10Vac|
|VDD1||VDD1||For driver logic supply.|
3.3V is available, please ask.
|VDD2||VDD2||Grid / Anode Supply||12Vdc to 72Vdc|
|EC||G||For static drive type only|
|EK||–||Filament bias voltage||0V to 10V|
|GND||VSS||Ground of VDD1 and VDD2||Ground 0V|
2.1 Filament Supply “Ef” and Bias Voltage “Ek”
Applying the correct filament voltage is the most important factor in extending the life of the VFD. Details on drive techniques and the filament bias voltage Ek required for the filament can be found in the application note on basic VFD operation.
2.2 Logic Supply Voltage “VDD1”
The logic supply voltage is supplied to the logic circuit of the built-in drivers. Normally, +5V voltage is applied across terminals “VDD1” and “VSS”. Always insert a noise filtering ceramic capacitor (0.01 to 0.22 uF) between VDD1 and VSS terminals in order to avoid false operations due to noise. Some types of VFD come with two pairs of “VDD1” and “VSS”, as shown in Figure 7. In this case, apply the power to all the terminals of the two pairs and insert the filtering capacitor separately across each of the “VDD1” and “VSS” pairs.
Fig. 7 Noise Filtering Capacitor for VDD1
2.3 Display Supply Voltage “VDD2” and R1
This power is supplied to the drivers for the display. Its voltage is applied to the internal grids and anodes through the driver outputs. For this type of VFD, +12V to +72V voltage is applied across the terminals “VDD2” and “VSS”. The voltage defined in each individual specification should be applied. The rated value of this display supply voltage will have been calculated for optimized luminance and lifetime assuming the most standard service conditions . This voltage may be varied within the specified rated voltage range in order to adjust the basic brightness of the VFD (see note below). When low power consumption is required, the display supply voltage can be held low, with the resulting effect on brightness. Please contact our technical department to discuss this type of requirement as too low a voltage will result in uneven brightness. If you plan to control the brightness by software, it is suggested that you adjust it by varying the pulse width of the blanking input described later, and not by controlling the display supply voltage.
It should be noted that some multiplexed grid anode independent type CIG VFDs come equipped with two “VDD2” terminals, namely, “VDD2G” dedicated to grid drivers, and “VDD2A” for the anode drivers. Normally the same voltage is applied to “VDD2G” and “VDD2A”, but some graphic type CIG VFDs may need to be supplied different voltages. Please check the individual specification for detail.
Many CIG VFDs require a current limiting resister in the VDD2 line in order to avoid false operation due to current surge. The resistance value of R is about 22 ohms. Please check the exact recommended value in each specification sheet.
Do not connect a capacitor between VDD2 at the display and Ground (0V) as this will invalidate the resistor.
2.4 Grid Voltage “Ec” (for Static Drive Type only)
The grid voltage is applied to terminal “G” in a static drive type CIG VFD.(Figure 8) The rating of “Ec” on the specification represents the voltage between terminal “G” and the center-tap of the filament transformer (F.C.T.), and does not include the filament bias voltage “Ek”.
This means the base level of “Ec” and “VDD1 “,”VDD2” are different on the specification.
Normally, the same voltage “VDD2” can be applied to the terminal “G” directly. But in certain cases, the required voltage for “Ec” may be different from “VDD2”.
Please refer to the “Block Diagram” on the specification which shows how to connect the voltage for the “Ec” and the other supply voltages.
Fig.8 Grid Voltage
2.5 Power Supply Sequence
While the display power is being supplied, if the logic supply voltage “VDD1” is floating, or is kept at less than “+4.5V”, the driver chips may be PERMANENTLY DESTROYED. Special care must be taken with the power supply SEQUENCE when the system is switched on or off. Please FOLLOW the sequence in Fig. 9 when switching the power on and off.
Fig. 9 – Power Supply Sequence and Safety Circuit
Power On: “VDD1” and “VDD2” should be ON at the same time, or “VDD2” should be ON after “VDD1” is ON.
Power Off: “VDD1” and “VDD2” should be OFF at the same time, or “VDD1” should be OFF after “VDD2” is OFF.
In other words, this means ” NEVER apply VDD2 without VDD1 “.
This can be achieved by putting a suitable PNP transistor in the VDD2 supply after any capacitors and controlling it’s turn on from the presence of 5V as shown in the circuit of Fig. 9.
There is no specific restriction on the on/off timing of the filament power, it may take one second for the filament to raise its temperature to the optimum value after the filament voltage “Ef” is turned on. Before this time period is reached, no segments can be illuminated.
3. CIG VFD Interfacing
3.1 Interface Signals
The interface of all CIG VFDs is “C-MOS” synchronous serial data.
The adjacent table lists the functions of the interface signals. The input voltage levels are 2.4V minimum for High and 0.7V maximum for Low with respect to Vss (0V) when VDD1 is 5V.
|Signal||Function *only where applicable|
|CLK||Shift Register Clock||Serial Data Read and |
Shift at Rising Edge
|GCLK||Shift Register Clock for the Grid Driver *|
|SI||Serial Data Input||H=ON, L=OFF|
|GSI||Serial Data Input for the Grid Driver *|
|SO, GSO||Serial Data Output||Used forwatchdog|
|LAT||Data Latch Control||H=Transparent,|
|GLAT||Data Latch Control for the Grid Driver *|
|BK||Driver Output Blanking Control||H=Output OFF, |
|GBK||Grid Driver Output Blanking Control *|
3.2 Interface Timing
The CLK input of the CIG driver shows a cycle time of 500ns equating to a 2MHz clock. Improvements have enabled clock rates up to 8MHz to be possible, but the interconnection method and interference may not support this speed. Please check the specification, minimize signal over-shoot, cross-talk and noise to prevent spurious data errors.
In most applications the latch signal is applied when the data clock is idle (H)igh since any positive going cross-talk spike will not cause a false clock.
Fig. 10 – Interface Timing of CIG Driver
3.2.1 Static Drive Type
For static drive, control the CIG VFD from a Serial I/0 as shown in Fig. 11.
A standard CPU is sufficient and due to the relatively low software overhead, it is also possible to control the CIG VFD by a standard parallel I/0 port.
Since there is no multiplex drive, the latch and blanking can be connected unless brightness control is required.
Fig.11 Application Circuit for Static Drive
3.2.2 Multiplex Drive Type
To achieve a sufficient refresh rate, assign at least one serial I/0 port exclusively for controlling the CIG VFD. Fig. 12 shows an example of the independent grid/anode type, but can be used for the hybrid interlaced grid/anode type as well.
In case the CPU is interrupted for some reason during multiplex driving, the grid scan may stop. This will cause permanent damage to the CIG VFD.
To protect the VFD, create a watchdog protection circuit which detects the grid scanning operation and will initiate grid blanking or switch off the display supply voltage “VDD2”. Fig. 12 gives an example of a protection circuit using a monostable and OR gate. When the grid scan serial data output of “GSO” is interupted, the monostable is no longer re-triggered and “GBK” sets “High” so that all driver outputs will be OFF.
Fig.12 Application Circuit for Multiplex Drive Type
4. Control Procedure
4.1 Static Drive
Figure 13 shows the data transfer protocol for a custom designed CIG VFD and is statically driven with one 96 bit driver. In a static driven CIG VFD, each input data bit of the shift register drivers is assigned to an anode segment in a one-on-one basis. The relevant assignment order is explained in the section called “Serial Data Format” or “Shift-Register Segment Assignment” in the individual specification.
Each segment is controlled by sending data bits as “High” for ON or “Low” for OFF. The pattern data can be stored in output registers (latches) by applying the latch pulse so that the current pattern can be displayed while a new set of serial bits is clocked in for the next pattern. The data stream for a static drive display need only be active when the illuminated pattern has to change making it suitable for low RFI applications in radio and measuring instruments.
Figure 13 – Static Drive Data Transfer with a 96 bit driver
4.2 Multiplex Grid-Anode Hybrid Interlace Drive
The example display pattern shows a 2 line, 20 character 5×7 dot matrix VFD with underline cursors. The electrodes consist of 20 grids and 2 x 36 anodes which totals 92 driver outputs. Since the driver has 96 outputs, 4 bits * are left unassigned and can be set High or Low.
Bit 1 is sent first (G1) through to bit 96 (A1).
Fig.14 Example of Shift Register Map for the Hybrid Interlace Type
The controlling CPU has the task of sending 20 x 96 bits every refresh cycle (TR).
In each of the 20 time slots T1 to T20, the corresponding Grid bit is set High to provide a sequential scan of all the grids.
Anode data bits are also configured for the desired pattern at the enabled grid.
Fig.15 Timing Chart Example for Grid Anode Hybrid Interlace Type
4.3 Multiplex Grid-Anode Independent Drive
In this example, a 2 line by 20 character 5×7 dot matrix display has 2 separate 96 bit drivers assigned to the 20 grids and the 2×36 anodes.
In this case the grid driver has 76 un-assigned outputs and the anode driver has 24 un-assigned outputs.
Fig.16 Example of Shift Register Map of the Grid Anode Independent Type
Semi-automatic grid scanning is achieved by setting GS1 to High for the first GCLK pulse then low for the rest of the refresh period. GLAT can be held High to allow the grid shift register data to be directly transferred to the grid outputs.
Time period Tn is expanded to show the 2×36 bits of anode data are clocked in, latched and then displayed in time period Tn+1.
Fig.17 Timing Chart Example for Grid Anode Independent Type
4.4 Overlapping Grid Scan for Graphic Displays
Most graphic dot matrix CIG VFDs require a particular scan procedure known as ‘overlapping grid scan’. This occurs when the space between anodes is small and it is necessary to turn on 2 adjacent grids at the same time in order to produce an even electron flow and consequently an even illumination of the anodes at the center of the adjacent grids.
There are several combinations of anode that can be used. Fig 18 and Fig 19 show the 4 way and 8 way schemes.
In the 4 way scheme, when Grid 1 and 2 are ON, anodes B+C are active. Then, when Grid 2 and 3 are ON, anodes D+A are active.
Fig. 18 – 4 Way Anode Separation
Each grid has 2 columns of anodes.
There are 4 sets of anodes ABCD
Fig. 19 – 8 way Anode Separation
Each grid has 4 columns of anodes.
There are 8 sets of anodes ABCDEFGH
4.4.1 Double Anode Driver Scheme
Fig. 20 – Block Diagram for MN12832E Double Anode Driver
To simplify the user circuit, the A+D and B+C anodes are controlled by two separated anode drivers with their serial data, clock and latch signals common and their blanking inputs BK1 and BK2 separately controlled to act as chip select (/CS) inputs. Although identical anode data is sent to both drivers, only the desired A+D or B+C driver is selected according to the pair of adjacent grids which are active. This sequence can be identified in the table below.
|Grids to be|
|Grid Driver Outputs||Blanking|
|T1||G64+G1||H||L||L||L||L||L||L||L||L||L||H||L||H||A and D|
|T2||G1+G2||H||H||L||L||L||L||L||L||L||L||L||H||L||B and C|
|T3||G2+G3||L||H||H||L||L||L||L||L||L||L||L||L||H||A and D|
|T4||G3+G4||L||L||H||H||L||L||L||L||L||L||L||H||L||B and C|
|T5||G4+G5||L||L||L||H||H||L||L||L||L||L||L||L||H||A and D|
|T61||G60+G61||L||L||L||L||L||L||H||H||L||L||L||L||H||A and D|
|T62||G61+G62||L||L||L||L||L||L||L||H||H||L||L||H||L||B and C|
|T63||G62+G63||L||L||L||L||L||L||L||L||H||H||L||L||H||A and D|
|T64||G63+G64||L||L||L||L||L||L||L||L||L||H||H||H||L||B and C|
|T1||G64+G1||H||L||L||L||L||L||L||L||L||L||H||L||H||A and D|
The diagram below shows the 64 time periods T1-T64 representing one refresh cycle TR.
Two High data bits are applied to SIG at the start of the cycle which provide the required adjacent grid turn on sequence above. Time slot Tn is expanded to show how 64 anode data bits are clocked into the shift registers from SI1 and SI2, then the LAT pulse latches the data ready to be displayed in time slot Tn+1. It can be seen that the idle state of the clocks is High.
Fig 21. Timing for the Double Anode Drivers of MN12832E
4.5 Blanking Control
The driver of the CIG VFD has a display blanking function to allow the driver outputs to be turned on and off. This enables control of the display on/off state, display brightness level and inter digit blanking to prevent ghost illumination when data latch is activated during multiplex driving.
When BK is ‘High’ the outputs are disabled and when BK is ‘Low’ the outputs are enabled.
To avoid data error during blanking control,
Do not change BK while writing data
Do not change BK while CLK is Low
Do not change CLK from Low to High while LAT is High and BK is Low.
When the brightness is adjusted by the blanking function using pulse width control in a static driven VFD, the pulse of the signal needs to have a frequency of at least 90Hz in order to avoid a flickering display. In a multiplexed display, the inter digit blanking pulse can be extended to provide brightness reduction.
Brightness = (T-tBK) / T x 100 (%) (Case of no blanking is 100%)
Fig.23 Brightness Control by Blanking
When applying power to the VFD, the blanking should be disabled to ensure random data in the shift registers does not cause a bright flash or current surge. Depending on the control procedure, the display should only be illuminated once the correct data is in the shift registers and one latch pulse has occurred.
5. Custom Design Guidance
Many aspects of custom design CIG VFD are identical to conventional VFD. This section aims to clarify the differences.
5.1 Lead Pins
The standard lead pin of the CIG VFDs is 6.0mm length and 2.0mm pitch. The dimensions of standard lead pin are shown in Fig. 24. Custom lead pin design is also available upon request.
Fig 24. CIG VFD Lead Pins
5.2 Anode and Grid Size
The area of a segment must not exceed 300mm2 due to the limited current output capacity of the driver chip. When a large segment is required, it should be divided into two or three parts with each assigned to a different driver. A similar condition applies to grid size. Please consult our technical department for advice.
5.3 Driver Selection
The table shows the available CIG drivers and the maximum voltages (VDD2) including filament bias voltages.
Optimize your design for the minimum number of devices to reduce the application cost.
|Driver||Number of Bit||Maximum Operating Voltage (VDD2)|
|Type 1||96 bit||43V MAX, 58V MAX|
|Type 2||64+64 bit||72V MAX|
|Type 3||4×32+16bit||72V MAX with grey scale control|
5.4 Semi Custom Design
Saving in tooling cost and development time can be achieved by using pre-prepared metal parts and substrate.
Please consult our design guidance on this subject.
6. Reliability Test Conditions
Basically the CIG VFD is subjected to the same reliability test standards “TT-90-3050A” as the conventional VFDs.
For details on the test conditions, refer to Vacuum Fluorescent Display Application Note APN1O1.
- Since the CIG VFD contains C-MOS chips, please be cautious of electrostatic discharge failure.
- Unpacking of the CIG VFD from the packing tray, mounting or soldering to the PCBs should be conducted in an environment provided with anti-static measures.
- When the SO and GSO terminals are not used, please leave them open.
- Some types of CIG VFDs may come equipped with terminals of the same designation.
- Those terminals with the same designation should all be connected in parallel.
- Be careful not to apply the display supply vantage (VDD2) without the logic supply voltage (VDD1).
- Please refer to the power supply sequence in this application note or individual specification.
- Insert a noise filtering capacitor between “VDD1” and “VSS”.
- When powering up the VFD, only illuminate the display when any random data in the driver is removed.
- To avoid a flickering display, the refresh rate must be 120Hz or higher.
- The grid scan must be continuous, and never be interrupted while the VFD is operating. If the grid scan is interrupted even momentarily, the VFD may be permanently damaged. See the protection circuit in Fig. 12.
8. Words used In Specifications
The “Spec No.” shows the revision number for the specification sheet. Each documented specification carries an area of revision history in the upper right corner of the top page. The specifications of the standard models are subject to change without prior notice, so, please check if the revision number of your specification is the latest version before evaluating it.
Absolute Maximum Ratings
The “Absolute Maximum Ratings” refer to values that must not be exceeded in any event. Using a VFD in excess of the specified rating may lead to its permanent breakdown. Therefore, high reliability will be secured if special attention is paid to the design of a power supply circuit, possible fluctuations in the supply voltage, surrounding components, operating temperature, environment surges or spikes, etc.
Rating or Recommended Operating Conditions
The “Rating” or “Recommended Operating Conditions” represent the specification of a recommended operating condition that guarantees the operation of the VFD. It also serves as a test condition for which the product is subjected prior to shipment from the factory. Therefore, it should be noted that if a VFD is used in excess of the maximum or minimum rating specified here, its operation and quality will not generally be guaranteed even when it remains within the absolute maximum rating.
In addition, this rated value has been defined assuming the most standard service conditions by users. However, some may want to study the possibility of using the VFDs outside the rated value, prompted by a desired individual requirement. In such a case, please feel free to consult with us, as we may be willing to discuss the possibility of the proposed specifications.
It shows how to connect the power supplies. The basic circuit used in factory inspection is the same as this one.
Electrical (and Optical) Characteristics
All of numbers specified in this section shows the characteristics when the CIG VFDs are tested under the typical (TYP) operating conditions unless otherwise noted.
It shows the AC characteristics and relationship of interface operations.
Serial Data Format
It shows the shift register and segment or grid assignment, and how to control these data to optimize grid scan.